Formal Verication of Behavioural Vhdl Specications : a Case Study

This paper addresses the problem of formally verifying VHDL descriptions. More precisely, we check the correctness of a VHDL architecture w.r.t. another architecture of the same entity. Both of them are translated into recursive functional forms, and the proof of their equivalence is realized by means of the Boyer-Moore theorem prover. Our methodology is illustrated by a signi cant example that has been proposed by THOMSON. This benchmark presents interesting characteristics and its proof is not obvious.